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\newacro{ALU}[\AC@hyperlink{ALU}{ALU}]{Arithmetic Logic Unit}
\newacro{ASCII}[\AC@hyperlink{ASCII}{ASCII}]{American Standard Code for Information Interchange}
\newacro{ASIC}[\AC@hyperlink{ASIC}{ASIC}]{Application-Specific Integrated Circuit}
\newacro{BCD}[\AC@hyperlink{BCD}{BCD}]{Binary Coded Decimal}
\newacro{BDD}[\AC@hyperlink{BDD}{BDD}]{Binary Decision Diagram}
\newacro{BIOS}[\AC@hyperlink{BIOS}{BIOS}]{Basic Input/Output System}
\newacro{BLIF}[\AC@hyperlink{BLIF}{BLIF}]{Berkeley Logic Interchange Format}
\newacro{CAT}[\AC@hyperlink{CAT}{CAT}]{Computer-Aided Tools}
\newacro{CISC}[\AC@hyperlink{CISC}{CISC}]{Complex Instruction Set Computer}
\newacro{CPU}[\AC@hyperlink{CPU}{CPU}]{Central Processing Unit}
\newacro{DRAM}[\AC@hyperlink{DRAM}{DRAM}]{Dynamic Random Access Memory}
\newacro{DUT}[\AC@hyperlink{DUT}{DUT}]{Device Under Test}
\newacro{EBCDIC}[\AC@hyperlink{EBCDIC}{EBCDIC}]{Extended Binary Coded Decimal Interchange Code}
\newacro{EDA}[\AC@hyperlink{EDA}{EDA}]{Electronic Design Automation}
\newacro{FSM}[\AC@hyperlink{FSM}{FSM}]{Finite State Machine}
\newacro{HDL}[\AC@hyperlink{HDL}{HDL}]{Hardware Description Language}
\newacro{IC}[\AC@hyperlink{IC}{IC}]{Integrated Circuit}
\newacro{IEEE}[\AC@hyperlink{IEEE}{IEEE}]{Institute of Electrical and Electronics Engineers}
\newacro{KARMA}[\AC@hyperlink{KARMA}{KARMA}]{KARnaugh MAp simplifier}
\newacro{LED}[\AC@hyperlink{LED}{LED}]{Light Emitting Diode}
\newacro{LSB}[\AC@hyperlink{LSB}{LSB}]{Least Significant Bit}
\newacro{LSN}[\AC@hyperlink{LSN}{LSN}]{Least Significant Nibble}
\newacro{MSB}[\AC@hyperlink{MSB}{MSB}]{Most Significant Bit}
\newacro{MSN}[\AC@hyperlink{MSN}{MSN}]{Most Significant Nibble}
\newacro{NaN}[\AC@hyperlink{NaN}{NaN}]{Not a Number}
\newacro{OER}[\AC@hyperlink{OER}{OER}]{Open Educational Resource}
\newacro{PCB}[\AC@hyperlink{PCB}{PCB}]{Printed Circuit Board}
\newacro{POS}[\AC@hyperlink{POS}{POS}]{Product of Sums}
\newacro{PROM}[\AC@hyperlink{PROM}{PROM}]{Programmable Read-Only Memory}
\newacro{RAM}[\AC@hyperlink{RAM}{RAM}]{Random Access Memory}
\newacro{RISC}[\AC@hyperlink{RISC}{RISC}]{Reduced Instruction Set Computer}
\newacro{ROM}[\AC@hyperlink{ROM}{ROM}]{Read Only Memory}
\newacro{RPM}[\AC@hyperlink{RPM}{RPM}]{Rotations Per Minute}
\newacro{RTL}[\AC@hyperlink{RTL}{RTL}]{Register Transfer Language}
\newacro{SECDED}[\AC@hyperlink{SECDED}{SECDED}]{Single Error Correction, Double Error Detection}
\newacro{SOP}[\AC@hyperlink{SOP}{SOP}]{Sum of Products}
\newacro{SDRAM}[\AC@hyperlink{SDRAM}{SDRAM}]{Synchronized Dynamic Random Access Memory}
\newacro{SRAM}[\AC@hyperlink{SRAM}{SRAM}]{Static Random Access Memory}
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\newacro{TTL}[\AC@hyperlink{TTL}{TTL}]{Transistor-Transistor Logic}
\newacro{USB}[\AC@hyperlink{USB}{USB}]{Universal Synchronous Bus}
\newacro{VHDL}[\AC@hyperlink{VHDL}{VHDL}]{VHSIC Hardware Descriptive Language}
\newacro{VHSIC}[\AC@hyperlink{VHSIC}{VHSIC}]{Very High Speed Integrated Circuit}
\newacro{VLIW}[\AC@hyperlink{VLIW}{VLIW}]{Very Long Instruction Word}
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